IP core application platformPhysical Library
Standard Cell Process Description Status
SMIC 40nm LL 9T standard cell library with multi-vt and multi-channel length Silicon proven
SMIC 40nm LL 12T standard cell library with multi-vt and multi-channel length Design Finish
GSMC 180nm Cost Effective 5.0V 7T standard cell library Design Finish

Memory Compiler Process Description Feature Word Range Bit Range Max Density Status
SMIC 40nm LL 1.1V Single Port SRAM Compiler(Low Power) Bit Write
Redundancy
Power Gating
Write Through
Self-time Bypass
LVT Periphery
256 ~ 32768 2~144 1152K bits Design Finish
Silicon Test on going
SMIC 40nm LL 1.1V One Port register files Compiler(Low Power) Bit Write
Power Gating
Write Through
Self-time Bypass
LVT Periphery
8~2048 2~144 72K bits Design Finish
Silicon Test on going
SMIC 40nm LL 1.1V One Port register files Compiler(High Speed) Bit Write
Power Gating
Write Through
Self-time Bypass
LVT Periphery
8~2048 2~144 72K bits Design Finish
Silicon Test on going
SMIC 40nm LL 1.1V Two Port register files Compiler(Low Power) Bit Write
Power Gating
Self-time Bypass
LVT Periphery
8~2048 2~144 72K bits Design Finish
Silicon Test on going
SMIC 40nm LL 1.1V Dual Port SRAM Compiler(Low Power) Bit Write
Redundancy
Power Gating
Write Through
Self-time Bypass
LVT Periphery
128~16384 2~72 288K bits Design Finish
Silicon Test on going
SMIC 40nm LL 1.1V Low Power via ROM Compiler Power Gating 256~65536 2~256 2M bits Design Finish
Silicon Test on going
TSMC 28nm LP 1.05V Single Port SRAM Compiler(Low Power) Bit Write
Redundancy
Power Gating
Write Through
Self-time Bypass
LVT Periphery
BIST, Pipe Line, Scan Chain
256 ~ 32768 2~144 1152K bits Design Finish
TSMC 28nm LP 1.05V Two Port register files Compiler(Low Power) Power Gating
Self-time Bypass
LVT Periphery
BIST, Pipe Line, Scan Chain
4~256 2~144 36K bits Design Finish
TSMC 28nm LP 1.05V Low Power via ROM Compiler Power Gating
BIST, Pipe Line, Scan Chain
32~65536 2~256 2M bits Design Finish
TSMC 28nm LP 1.05V Dual Port SRAM Compiler(6T Cell) Bit Write
Redundancy
Power Gating
Write Through
Self-time Bypass
LVT Periphery
BIST, Pipe Line, Scan Chain
256~16384 2~72 288K bits Design Finish
TSMC 28nm LP 1.05V One Port register files Compiler(Low Power) Bit Write
Power Gating
Write Through
Self-time Bypass
LVT Periphery
BIST, Pipe Line, Scan Chain
8~2048 2~144 72K bits Design Finish
TSMC 28nm LP 1.05V One Port register files Compiler(High Speed) Bit Write
Power Gating
Write Through
Self-time Bypass
BIST, Pipe Line, Scan Chain
8~2048 2~144 72K bits Design Finish
SMIC 40nm LL 1.1V ultra High Speed Single Port SRAM Compiler Bit Write
Write Through
Self-time Bypass
128~8192 2~96 192K bits Design Finish
GSMC 153nm Generic 1.8V ultra tiny Single Port SRAM Compiler Bit Write
Self-time Bypass
Write Through
256~32768 2~128 1M bits Design Finish (4 instances)
GSMC 180nm Cost Effective 5.0V standard diffusion ROM Compiler   128~16384 2~128 512K bits Design Finish
GSMC 180nm Cost Effective 5.0V standard single port SRAM Compiler Bit Write
Self-time Bypass
Write Through
8~16384 2~128 256K bits Design Finish
180nm RASP/RADP   8K 128 512K Silicon Proven
RFSP/RFTP   1K  256 64K Silicon Proven
DROM/LPDROM   32K 128 2M Silicon Proven
VROM/LPVROM   32K 128 2M Silicon Proven
LPRASP   8K 128 512K Silicon Proven
130nm RASP/RADP   8K 128 512K Silicon Proven
RFSP   512 256 32K Silicon Proven
RFTP   1K  256 64K Silicon Proven
DROM/LPDROM   16K 128 1M Silicon Proven
VROM/LPVROM   16K 128 1M Silicon Proven
ULPRASP   16K 128 512K Silicon Proven
ULL Memory Series   / / / Silicon Proven
HSRASP   4K 128 128K Silicon Proven
90nm RASP   16K 64 512K Silicon Proven
RADP   8K 128 256K Silicon Proven
RFSP   512 256 32K Silicon Proven
RFTP   1K  256 64K Silicon Proven
VROM   32K 128 2M Silicon Proven
HCRFSP   1024 256 64K Design Finish
65nm HSRASP   8K 32 256k Silicon Proven
LPRASP   32K 16 512K Silicon Proven
Dcache(CAMRAM)   512 256+patities 16KB Silicon Proven
Lcache(CAMRAM)   512 256+patities 16KB Silicon Proven
55nm HSRASP   8K 32 256k Silicon Proven
LPRASP   32K 16 512K Silicon Proven
Dcache(CAMRAM)   512 256+patities 16KB Design Finish
Lcache(CAMRAM)   512 256+patities 16KB Design Finish

IO Process Part Number IO Pitch(W*L,um²) Pad Head(W*L,um²) Top Metal Status
180nm S18_DUPIO_01 60*121 50*90 M5/6 Silicon Proven
G18_DUPIO_01 60*121 51*90 M5/6 Silicon Proven
S18_ANALOGIO_DUP_05 75*117 66*97 M5/6 Silicon Proven
S18_MULTIO_DUP_07 65*135 56*90 M5/M6 Silicon Proven
130nm S13_DUPIO_01 70*108 61*66 M6/7/8 Silicon Proven
S13_ANALOGIO_DUP_05 60*108 51*73 M6/7/8 Silicon Proven
S13_MULTIO_DUP_05 60*108 51*73 M6/7/8 Silicon Proven
S11_MULTIO_DUP_06 75*126 51*73 M6 Silicon Proven
S11_SSTLCOMBO_02(stagger DUP) 35*286 51*51 M6/8 Silicon Proven
S11_ONFICOMBO_DUP_02 80*115 51*73 M6 Silicon Proven
地址:上海市徐汇区宜山路333号汇鑫大厦1号楼1704室   邮编:200030
ADD:Rm1704,HUIXIN Building,333yishan Rd,Shanghai,P.R.China, 200030
TEL:86-21-61154610    86-21-61154686
FAX:86-21-61154601