Patent Analysis Report on CPU Native big.LITTLE Technology

Patent Analysis Report on CPU Native big.LITTLE Technology

• Table of contents

Chapter 1：Overview of big.LITTLE technology
1.1 Research background
1.2 Problems in implementing big.LITTLE : a case study of Arm
Chapter 2：Arm CPU big.LITTLE technology
2.1 Development and current status of Arm big.LITTLE technology
2.2 Software execution model for big.LITTLE task scheduling
2.3 Software switch controller
Chapter 3：big.LITTLE technology in Intel pocessors
3.1 Development path of Intel performance hybrid technology
3.2 Intel performance hybrid architecture
3.3 Hardware and software support for Intel performance hybrid architecture
Chapter 4：Patent analysis of Arm big.LITTLE technical
4.1 Patent overview of Arm CPU big.LITTLE technology
4.2 Task scheduling
4.3 Transaction processing optimization
4.4 Power control: delegating component power control
4.5 Secure and reliable applications
Chapter 5：Patent analysis of Intel big.LITTLE technology
5.1 Patent overview of Intel big.LITTLE technology
5.2 Task scheduling
5.3 Power consumption and power control
5.4 Heterogeneous instruction set architecture
5.5 Structural consistency
5.6 Cache coherency
5.7 processes and structure of devices
5.8 big.LITTLE applications: managing hardware errors in a multi-core environment

• Introduction

In 2011, when Arm introduced the Cortex-A7, it first launched the “big.LITTLE” technology, which connects high-performance “big” CPU clusters and high-efficiency “small” CPU clusters through Cache Coherent Interconnect(CCI). In 2017, Arm launched its evolved technology “DynamIQ big. LITTLE” technology, allowing the mixing of big cores and LITTLE cores in a cluster, and achieving the task migration between them through the DynamIQ Shared Unit (DSU). Arm’s big.LITTLE technology as one of the power management technologies, working in coordination with DVFS, clock gating, and temperature management to comprehensively control the power consumption of the SoC.
In 2019, Intel also unveiled a heterogeneous technology similar to Arm big.LITTLE technology – Intel Hybrid Technology. Based on this, Intel further developed the “Intel performance hybrid architecture”, which added a "Intel Thread Director" to monitor and build intelligent scheduling solutions directly in the cores. In Intel’s processors, the big cores are called the performance cores (P-cores), and the LITTLE cores are called the efficiency cores (E-cores).
Based on the study of the core issues faced by big.LITTLE technology, this report first reviews the respective big.LITTLE technologies of Arm and Intel in Chapters 2 and 3, including the evolution of their big.LITTLE architectures, and focuses on the key components for task scheduling - Arm's switch controller and Intel thread director. The report then analyzes every relevent patents applied by Arm and Intel in China and the United States over the past five years (2017-2022.6), clarifying the technical issue,technical solutions and technical effects, and classifying the technology. Chapter 4 focuses on Arm, and through patent analysis, it can be seen that Arm patented technology of big.LITTLE technology mainly involves task scheduling, and also involves transaction processing optimization, power control and ecurity application. Chapter 5 focuses on Intel, and it can be seen that Intel patent technology mainly focuses on the task scheduling strategy, power control, instruction set architecture processing and structural consistency of P-cores and E-cores, and the others are cache coherence, process and transistor structure improvement, specific application scenarios of P-cores and E-cores.

*The above contents is for reference only, please refer to the contents of patent analysis report for details.Thank you!

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Patent Analysis Report on CPU Native big.LITTLE Technology
Pages: 167
Price: $100,000

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