上海市集成电路高技能人才培养基地

集成电路设计培训课程


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IC system design and simulation Training and enrollment brochures

I、Training object

1、Personnel engaged in integrated circuit design(including fresh master's graduates).

2、Personnel engaged in IC Verification.

3、Staff engaged in FPGA design and silicon testing.

II、Training objectives

1、Master the use of the current mainstream verification language SystemVerilog in verification.

2、Proficient in validation methodology UVM.

3、Be able to apply SV to build a hierarchical verification platform independently.

4、It can independently use UVM to build a complete module level verification platform.

5、Be able to conduct case operation in combination with verification methodology and SV, fully master design specifications, formulate verification scheme, complete verification platform construction, develop test cases, verification execution and coverage acceptance.

6、Refer to the verification process of first-class companies in the industry, and be able to complete relevant documents and pass the defense one by one.

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Advanced layout course arrangement

1. Differences and precautions between 28nm and 55nm process layout

2. Differences in process layout matching between 28nm and 55nm

3. Treatment of secondary effect of high-speed simulated layout in 28nm and 55nm processes

4. Layout design of bottom module and layout of fullchip

5. Several kinds of Eric errors that can wait

6. Layout processing and innovation of high speed analog layout PLL

7. Specification for layout processing of ESD drive tube

8. Precise placement of ADC sampling capacitors

9. Power layout of chip

10. Layout processing of ESD

32 class hours, 4 days in total

Contact information

Contacts:Gina Hong/021-61154610Cherie Su/021-61154610

E-mail:gina.hong@ssipex.com cherie.su@ssipex.com

Wechat:

 

IC Integrated circuit Layout Design Training and enrollment brochures

I、Training object

1、Science and engineering graduates with zero foundation of integrated circuit layout design (including microelectronics, physics, materials, computer and other related majors).

2、Relevant professionals who are willing to engage in integrated circuit layout design.

II、Training objectives

Junior Engineer: through the training, the zero foundation students fully master the knowledge and skills of IC layout design, become a qualified junior engineer and can undertake ordinary IC layout design.

III、Training features

1、Shanghai Silicon Intellectual Property Trading Center has a national excellent territory learning platform and hardware support, including the most advanced design tools and verification tools.

2、In order to ensure the training quality, learning courses and practical training are mainly offline, and homework, Q & A and extracurricular learning are assisted online.

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Digital circuit layout and wiring design (PR) Training and enrollment brochures

I、Training object

1、Junior designers engaged in IC back-end design and Implementation (including fresh master graduates(including fresh master's graduates).

2、Microelectronics industry practitioners interested in digital circuit layout and wiring design.

II、Training objectives

1、Master the current mainstream back-end layout and wiring tool.

2、Master the back-end layout and wiring method.

3、Be able to use circuit design and simulation tools.

4、It can independently complete the implementation process of back-end layout and wiring from net-list to GDSII.

III、Training features

1、Pay attention to the combination of theory and practice, focus on practical training skills, combine complete basic theoretical training, and guide practical training with reference to the verification process of front-line companies.

2、Formulation of physical implementation scheme: including data preparation, layout planning, clock tree synthesis and cabling design. Train designers to master the actual design process and cultivate the ability to independently undertake complex layout and wiring design.

3、Timing verification and physical verification: including static timing analysis process and physical verification DRC / LVS / ant / DFM process and inspection methods, so that students can master the strict verification process.

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Hardware and software design of field programmable gate array (FPGA) and heterogeneous system Training and enrollment brochures

I.Training object

1、Personnel who use FPGA devices for scientific research and product development

2、Interested in FPGA design or personnel in related fields;

3、Staff engaged in chip prototype verification.

II.Training objectives

1、Master the structure of FPGA and the principle of programmable development

2、Master the method of writing Verilog program, be able to design common digital circuit modules, verify digital circuit design with simulation tools, and optimize digital circuit timing design and power consumption design

3、Use tools to complete FPGA design and constraint file input, FPGA synthesis and debugging, timing analysis and case analysis, FPGA bit file generation, FPGA programming download and debugging

4、Generate a programmable hardware platform for embedded software development, use tools to run and debug the embedded software of zynq heterogeneous devices, configure and generate bootloader, run and analyze the execution process of bootloader, configure and generate Linux kernel and file system, and run and analyze the execution process of Linux operating system

5、Be able to use tools to debug high-level integrated input language C or C + + programs, use tools to design IP cores, analyze HLS results and design optimization, and use tools to design software and hardware programs of programmable heterogeneous systems

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Mirco-chip interface circuit simulation and test Training and enrollment brochures

I、Training object

1、Personnel engaged in integrated circuit design, manufacturing and other related industries(including fresh master's graduates).

2、Personnel engaged in IC packaging, testing and other related industries

3、Personnel engaged in PCB design, PCB manufacturing, smart card, equipment materials, system design and other related industries

II、Training objectives

1、Master the basic knowledge of chip interface circuit, and be able to use simulation tools to complete common circuit simulation

2、Master the Ibis modeling method of chip interface circuit model, and be able to use modeling tools to complete chip IBIS modeling and package parameter extraction

3、Master the test, verification and application of chip interface circuit IBIS model, and master the basic knowledge of signal integrity

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Mirco-chiptestability circuit design and simulation (DFT) Training and enrollment brochures

I、Training object

1、Personnel engaged in integrated circuit design(including fresh master's graduates).

2、Staff interested in integrated circuit DFT design and verification.

II、Training objectives

1、Understand the basic concept of IC testing, the basic principle of design for testability, and be familiar with the mainstream design for testability methods in the industry.

2、Master the boundary scan technology and be able to independently design the required hardware logic.

3、Master scan insertion technology and understand common fault tests such as stuck at, transit, path delay and IDDQ.

4、Understand the significance of on-chip clock control (OCC) for at speed test, and understand and master scan compression technology.

5、Master ATPG implementation technology, generate and verify test vectors.

6、Master MBIST implementation technology, perform MBIST logic insertion and verification.

7、Be able to combine the learned test methodology, design the testability structure of SOC chip, formulate test scheme, realize test structure, verify test results, collect coverage and estimate yield.

8、Understand the significance of MBIST diagnosis and scan diagnosis for improving chip manufacturing yield, and master the basic test and diagnosis process.

9、Be able to refer to the testable design verification process of first-class companies in the industry, complete relevant documents and pass the defense one by one.

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IC operational amplifier design and simulation Training and enrollment brochures

I、Training object

1、Personnel engaged in analog integrated circuit design(including fresh master's graduates).

2、Personnel interested in analog integrated circuit design.

II、Training objectives

1、Master the working principle of CMOS transistor.

2、Master the principle of operational amplifier.

3、Master the methods of stability and frequency compensation.

4、Be able to use EDA circuit design tool to design the schematic diagram and symbols of operational amplifier.

5、Be able to simulate the environment and operational amplifier with circuit design tools;

6、Can analyze the simulation results of operational amplifier.

III、Training features

* Pay attention to the combination of theory and practice, focus on training skills, combine complete basic theory training, and guide the training with reference to international advanced operational amplifier design methods.

1、This paper systematically introduces the working principle of CMOS transistor, the circuit principle of operational amplifier, the frequency analysis method of electronic circuit, the principle of feedback amplifier, the stability and frequency compensation method of amplifier, and the performance parameters of operational amplifier.

2、The schematic diagram and circuit symbols of operational amplifier are established by EDA design tool, and then the performance of operational amplifier is simulated by EDA simulation tool. Combination of theory and practical operation.

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运算放大器集成电路设计仿真培训招生简章

一、培训对象

1、从事模拟集成电路设计的工作的人员;

2、有意从事模拟集成电路设计的工作的人员。

二、培训目标

1、熟练掌握运算放大器原理,掌握稳定性和频率补偿的方法;

2、能够制作和使用跨导效率查找表;

3、能够应用Matlab来系统优化设计运算放大器电路;

4、能够用Cadence电路设计工具设计运算放大器的原理图和符号;

5、能够用Cadence ADE仿真环境和Spectre仿真器进行运算放大器仿真;

6、能够分析运算放大器的仿真结果。

三、培训特色

注重理论和实践的结合,着重实训技能结合完备的基础理论培训,参照国际先进的运算放大器设计方法来指导实训为特色。

1、系统地介绍运算放大器电路原理,电子电路的频率相信分析方法,反馈放大器原理,放大器稳定性和频率补偿方法,运算放大器的性能参数。先进的利用跨导效率来系统地设计运算放大器的方法,运用Matlab和Spectre来产生SPICE跨导效率查找表,通过查找表来确定MOS晶体管的尺寸。用跨导效率作为模拟电路设计折衷的中心变量,一些基于Matlab程序脚本的设计流程,可以方便快速准确地设计运算放大器各个MOS晶体管的尺寸。

2、利用Cadence IC设计工具建立运算放大器原理图和电路符号,再运用Cadence ADE和Spectre对运算放大器的性能进行仿真。理论与实践操作相结合。

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运算放大器集成电路设计仿真培训招生简章

一、培训对象

1、从事模拟集成电路设计的工作的人员;

2、有意从事模拟集成电路设计的工作的人员。

二、培训目标

1、熟练掌握CMOS晶体管工作原理

2、熟练掌握运算放大器原理

3、掌握稳定性和频率补偿的方法;

4、能够用Cadence电路设计工具设计运算放大器的原理图和符号;

5、能够用Cadence ADE仿真环境和Spectre仿真器进行运算放大器仿真;

6、能够分析运算放大器的仿真结果。

三、培训特色

注重理论和实践的结合,着重实训技能结合完备的基础理论培训,参照国际先进的运算放大器设计方法来指导实训为特色。

1、系统地介绍CMOS晶体管工作原理,运算放大器电路原理,电子电路的频率相信分析方法,反馈放大器原理,放大器稳定性和频率补偿方法,运算放大器的性能参数。

2、利用Cadence IC设计工具建立运算放大器原理图和电路符号,再运用Cadence ADE和Spectre对运算放大器的性能进行仿真。理论与实践操作相结合。

四、培训费用

1、培训费3000元(参考)。包含教材费、场地费、线上平台、实训账号等。

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